Memory Visibility and Ordering¶

In the presence of caches, compiler reordering, and out-of-order execution, writes by one thread are not immediately visible to others. A memory model defines when writes become visible and what ordering guarantees exist. The "happens-before" relation formalizes when one operation's effects are guaranteed visible to another.

Tension Addressed¶

Isolation vs. Performance

Recognizable As¶

Memory barriers/fences, volatile/atomic declarations, acquire-release semantics. Bugs manifest as stale reads, missing updates, or operations appearing out of order - often only on certain hardware or under load.

Canonical Sources¶

Lamport, "Time, Clocks, and the Ordering of Events in a Distributed System" (1978); Adve & Gharachorloo, "Shared Memory Consistency Models: A Tutorial" (1996)

Transfers To¶

Distributed systems (eventual consistency), database replication, CPU architecture