Instruction Pipelining¶

Processors overlap instruction execution in stages (fetch, decode, execute, write-back); this pipeline enables high throughput but creates dependencies and stall conditions. Pipeline hazards explain why certain code patterns are slow.

Tension Addressed¶

Predictability vs. Flexibility

Recognizable As¶

Instruction-level parallelism, pipeline stalls from data dependencies, why branches are expensive (pipeline flush), loop unrolling benefits.

Canonical Sources¶

Hennessy & Patterson, Computer Architecture: A Quantitative Approach; Fog, Optimizing software in C++

Transfers To¶

Compiler design, microservice architectures (analogous pipeline stages), stream processing

A pipeline is only as fast as its slowest stage, and breaks require refilling. This principle transfers: assembly lines, HTTP request pipelines, CI/CD pipelines all exhibit similar behavior.